— By means of a separate I/O address space (using
specific I/O instructions)
— By means of memory-mapped I/O (using general-purpose
operand manipulation instructions )
4.1.1. Separate I/O address space (An Isolated I/O)
— I/O devices treated separately from memory.
— The 80386 provides a separate I/O address space,
distinct from physical memory, that can be used to address the input/output
ports that are used for external 16 devices.
— Can be accessed as either byte-wide or word-wide.
— The I/O address space consists of
— 216 (64K) individually addressable 8-bit
ports;
— any two consecutive 8-bit ports can be treated as a
16-bit port;
— and four consecutive 8-bit ports can be treated as a
32-bit port.
Figure.1 I/O Mapped I/O
— Advantages:
- Provides a separate I/O address space, distinct from
physical memory
-
Special
instructions have been provided in the instruction set to perform isolated I/O input and output
operations.
-
These instructions
have been tailored to maximize I/O performance.
— Disadvantages:
- All input and output data transfers must take place
between AL or AX register and the I/O port.
4.1.2. Memory-mapped I/O
— I/O devices is placed in memory address space of the
microcomputer.
-The memory address space
is assigned to I/O devices.
- MPU looks at the I/O
port as though it is a storage location in memory.
- Make use of instructions
that affect data in memory rather than special input/output instructions.
Figure 2: Memory Mapped I/O
— Advantages:
-
Many more
instructions and addressing modes are available to perform I/O operations.
- I/O
transfers can now take place between I/O port and internal registers other than
just
AL/AX.
— Disadvantages:
-
Memory
instructions tend to execute slower than those specifically designed for
isolated I/O.
- Part of
the memory address space is lost.
4.2 Classes of I/O Instructions:
There are two classes of
I/O instruction:
1. Those that transfer a
single item (byte, word, or doubleword) located in a register. Known as “Register
I/O instructions”.
2. Those that transfer
strings of items (strings of bytes, words, or doublewords) located in memory.
These are known as "string I/O
instructions" or "block I/O instructions".
4.2.1. Register I/O Instructions
— The I/O instructions IN and OUT are provided to move
data between I/O ports and the EAX (32-bit I/O), the AX (I6-bit I/O), or AL
(8-bit I/O) general registers.
— IN and OUT instructions addresses I/O ports either
directly, with the address of one of up to 256 port
— Addresses coded in the instruction, or indirectly
via the DX register to one of up to 64K port addresses.
Input Output Instructions:
4.2.2. Block I/O Instructions
• The block (or string) I/O instructions INS and
OUTS move blocks of data between I/O
ports and memory space.
• Block I/O instructions
use the DX register to specify the address of a port in the I/O address space.
INS and OUTS use DX to specify:
-8-bit ports numbered 0 through 65535
-16-bit ports numbered 0, 2,4, ... , 65532, 65534
-32-bit ports numbered 0, 4, 8, ... ~ 65528, 65532
• Block I/O
instructions use either SI or DI to designate the source or destination memory
address.
• For each transfer, SI or DI are automatically either
incremented or decremented as specified by the direction bit in the flags
register.
4.3 Protection and I/O:
Two mechanisms provide
protection for I/O functions:
1.The IOPL field in the
EFLAGS register defines the right to use I/O-related instructions. (For detail
Ref. Page no. 8-4 of manual)
2. The I/O permission bit
map of a 80386 TSS segment defines the right to use ports in the I/O address
space. (For detail Ref. Page no. 8-5 )
- These mechanisms operate only in protected
mode, including virtual 8086 mode; they do not operate in real mode.
- In real
mode, there is no protection of the I/O space; any procedure can execute
I/O instructions, and any I/O port can be addressed by the I/O
instructions.
4.3.1 I/O Exceptions and Interrupts:
• Interrupts and exceptions are special kinds of
control transfer; they work somewhat like un-programmed CALLs.
• They alter the normal program flow to handle
external events or to report errors or exceptional conditions.
•
• The difference between interrupts and exceptions is
that interrupts are used to handle asynchronous events external to the
processor, but exceptions handle conditions detected by the processor itself in
the course of executing instructions.
There are two sources for
external interrupts and two sources for exceptions :
1. Interrupts
• Maskable interrupts,
which are signaled via the INTR pin.
• Nonmaskable interrupts,
which are signaled via the NMI (Non-Maskable Interrupt) pin.
2. Exceptions
• Processor detected.
These are further classified as faults, traps, and aborts.
• Programmed. The
instructions INTO, INT 3, INT n, and BOUND can trigger exceptions.
.These instructions are
often called "software interrupts", but the processor handles them as
exceptions.
4.3.2. Identifying Interrupts
- The processor associates an identifying number with each different
type of interrupt or exception.
- The NMI and the exceptions recognized by the processor are assigned
predetermined identifiers in the range 0 through 31.
- The identifiers of the maskable interrupts are determined by
external interrupt controllers (such as Intel's 8259A Programmable Interrupt
Controller) and communicated to the processor during the processor's
interrupt-acknowledge sequence.
- The numbers assigned by an 8259A PIC can be specified by software.
Any numbers in the range 32 through 255 can be used.
·
The assignment
of interrupt and exception identifiers.
4.3.3 Exceptions:
— Faults- Faults are exceptions that are reported
"before" the instruction causing the exception. Faults are either
detected before the instruction begins to execute, or during execution of the
instruction. If detected during the instruction, the fault is reported with the
machine restored to a state that permits the instruction to be restarted.
— Traps- A trap is an exception that is reported at
the instruction boundary immediately after the instruction in which the
exception was detected.
— Aborts- An abort is an exception that permits
neither precise location of the instruction causing the exception nor restart
of the program that caused the exception. Aborts are used to report severe
errors, such as hardware errors and inconsistent or illegal values in system
tables.
4.3.4 Enabling and Disabling Interrupts:
1. NMI Masks Further NMI’s
:
— While an NMI handler is executing, the processor
ignores further interrupt signals at the NMI pin until the next IRET
instruction is executed.
2. IF Masks INTR :
— The IF (interrupt-enable flag) controls the
acceptance of external interrupts signalled via the INTR pin. When IF=O, INTR
interrupts are inhibited; when IF=I, INTR interrupts are enabled. As with the
other flag bits, the processor clears IF in response to a RESET signal.
— The instructions CLI and STI alter the setting of IF
CLI (Clear Interrupt-Enable Flag) and STI (Set Interrupt-Enable Flag)
explicitly alter IF (bit 9 in the flag register). These instructions may be
executed only if CPL ~ IOPL. A protection exception occurs if they are executed
when CPL > IOPL. Continued..
3. RF Masks Debug Faults :
— The RF bit in EFLAGS controls the recognition of
debug faults. This permits debug faults to be raised for a given instruction at
most once, no matter how many times the instruction is restarted.
4.MOV or POP to SS Masks
Some Interrupts and Exceptions :
— Software that needs to change stack segments often
uses a pair of instructions;
for example: MOV
SS , AX
MOV ESP, StackTop
4.4 Priority Among Simultaneous
Interrupts and Exceptions:
— If more than one interrupt or exception is pending
at an instruction boundary, the processor services one of them at a time.
— The processor first services a pending interrupt or
exception from the class that has the highest priority, transferring control to
the first instruction of the interrupt handler.
— Lower priority exceptions are discarded; lower
priority interrupts are held pending.
— Discarded exceptions will be rediscovered when the
interrupt handler returns control to the point of interruption.
4.4.1 Interrupt Descriptor Table (IDT)
- The third table needed
for Intel386 DX systems is the Interrupt Descriptor Table.
- The IDT contains the
descriptors which point to the location of up to 256 interrupt service
routines.
- The IDT may contain
only task gates, interrupt gates, and trap gates.
- The IDT should be at
least 256 bytes in size in order to hold the descriptors for the 32 Intel
Reserved Interrupts.
- Every interrupt used by
a system must have an entry in the IDT.
- The IDT entries are
referenced via INT instructions, external interrupt vectors, and
exceptions.
Figure 3: Structure of IDT(Interrupt Descriptor
Table)
4.4.2 IDT Descriptors:
Figure 4: IDT Descriptors
4.5 Interrupt Tasks and Interrupt
Procedures:
— Just as a CALL instruction can call either a
procedure or a task, so an interrupt or exception can "call" an
interrupt handler that is either a procedure or a task.
— When responding to an interrupt or exception, the
processor uses the interrupt or exception identifier to index a descriptor in
the IDT.
— If the processor indexes to an interrupt gate or
trap gate, it invokes the handler in a manner similar to a CALL to a call gate.
— If the processor finds a task gate, it causes a task
switch in a manner similar to a CALL to a task gate.
4.5.1 Interrupt Tasks
— A task gate in the IDT points indirectly to a task,
as Figure illustrates. The selector of the gate points to a TSS descriptor in
the GDT.
4.5.2 Interrupt Procedures:
— An interrupt gate or trap gate points indirectly to
a procedure which will execute in the context of the currently executing task
as illustrated by Figure 9-4.
— The selector of the gate points to an
executable-segment descriptor in either the GDT or the current LDT.
— The offset
field of the gate points to the beginning of the interrupt or exception
handling procedure.
— The 80386 invokes an interrupt or exception handling
procedure in much the same manner as it CALLs a procedure; for the following
sections.
1 . STACK OF INTERRUPT
PROCEDURE
2. RETURNING FROM AN
INTERRUPT PROCEDURE
3. FLAGS USAGE BY INTERRUPT PROCEDURE
4. PROTECTION IN INTERRUPT PROCEDURES
4.6 Error Code:
·
With
exceptions that relate to a specific segment, the processor pushes an error
code onto the stack of the exception handler (whether procedure or task).
·
The format of
the error code resembles that of a selector; however, instead of an RPL field
The error code contains two one-bit items:
1. The processor sets the EXT bit if an event external to the
program caused the exception.
2. The processor sets the
I-bit (IDT-bit) if the index portion of the error code refers to a gate
descriptor in the IDT.
4.7 Exception Conditions:
