Interrupt and Exception MCQ in 80386DX
Q.1. In Error code format in 80386 the bit position
of TI bit is bit number _______.
a) 0 b) 1 c) 2 d)
3
Q.2. In Error code format in 80386, If the I-bit is
not set, the TI bit indicates whether the error code refers to the ____________.
a) GDT Value 1 b)
GDT Value 0 c) LDT
Value 0 d) None of
these
Q.3. In Exception condition in 80386, if condition checked for SS segment
selector is valid then ________ type of Exception is generated.
a) GP b)
NP c)
SF d)
TS
Q.4. The 80386 invokes an interrupt or exception
handling procedure in much the same manner as it _________ a procedure.
a) CALLs b)
Traps c) Gets d) JMP
Q.5. In IDT of 80386 ________ pointing to a TSS
descriptor in Interrupting Tasks.
a) Trap Gate b)
Interrupt Gate c) Task Gate d)None
of these
Q.6. In Interrupt Descriptor Table (IDT) the ISR
stands for ________________.
a) Interrupt Status Register b) Interrupt Service Routine c)
Interrupt Service Request d) None
Q.7. The
IDT contains the descriptors which point to the location of up to ___________.
a) 255 ISR b) 256 ISR c) 65535 ISR d) 65536
ISR
Q.8. The IDT
entries are referenced via _________, external interrupt vectors, and
exceptions.
a) INTO Instruction b)
INTR Instruction c) INTA Instruction d) INT instructions
Q.9. The
processor first services a _________________________.
a) A Pending Interrupts with highest priority
b) A pending Interrupt with lowest priority
c) A pending Interrupt with simultaneously
d) A pending Interrupt
Q.10. The _____ bit in EFLAGS controls the
recognition of debug faults in 80386.
a) IF b) SF c) RF d)
CF
Q. 11. The __________
controls the acceptance of external interrupts signaled via the INTR pin.
a) IF b) SF c) RF d)
CF
Answers:
Q.1. c) Q.2. b) Q.3. d) Q.4. a) Q.5.
c) Q.6. b) Q.7.
b) Q.8. d) Q.9. a)
Q.10. c) Q.11. a)
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