MCQ on I/O, Interrupt and Exception

MCQ on I/O, Interrupt and Exception

  2:03 AM    Dnyaneshwar Kudande

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UNIT-4 Input Output, Interrupt and Exception in 80386

1. In I/O addressing if value in DX type is used the port range is upto ________.

a) 255              b) 256              c) 65535                      d)65536

2. If the INT3 instruction is executed then which type of exception is executed?

a) Fault             b) Trigger         c) Abort                       d) None of these

3. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program

4. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit

5. While executing main program, if two or more interrupts occur, then the sequence of appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt

6. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability

7. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none

8. If any interrupt request given to an input pin cannot be disabled by any means then the input pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none

9. The INTR interrupt may be
a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none

10. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request

11. The INTR interrupt may be masked using the flag
a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag

12. When hardware is accessed by reading and writing to the specific memory locations, then it is called
a) port-mapped I/O
b) controller-mapped I/O
c) bus-mapped I/O
d) none of the mentioned

13. In memory-mapped scheme, the devices are viewed as
a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices

14.  The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read

15. The operation, IOWR (active low) performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data

Answers:

1.c)      2.b)      3.c)      4.a)      5.d)      6.c)      7.a)      8.b)      9.a)      10.b)    11.c)     12).d)      13.b)
14.c)    15.b)