Multiple Choice Questions (MCQ's)

Multiple Choice Questions (MCQ's)

  5:57 AM    Dnyaneshwar Kudande

---

80386 Microprocessor
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Introduction to 80386 Microprocessor”

Question 1
80386DX is a _______ bit microprocessor?
Option A. 16                 Option B.20
Option C.32                  Option D.64
Correct Answer C

Question 2
ALU of 80386DX is ______bit.
Option A.16                 Option B.20
Option C.30                 Option D.32
Correct Answer D

Question 3
The 803806DX can address upto _________ vitual memory
Option A.1 TeraByte     Option B.64 TeraByte
Option C.16 TeraByte   Option D.8TeraByte
Correct Answer B

Question 4
The 803806DX can address upto _________ physical memory
Option A.1 MB          Option B.64 MB
Option C.16 GB         Option D.4 GB
Correct Answer D

Question 5
_________ Unit of 803806DX microprocessor reads instruction from memory.
Option A. Execution unit               Option B.Decode Unit
Option C.Prefetch unit                  Option D.Control Unit
Correct Answer C

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Architecture and Signal Descriptions of 80386”.

1. Which of the units is not a part of internal architecture of 80386?
a) central processing unit          b) memory management unit
c) bus interface unit                  d) none of the mentioned View Answer
Answer: d Explanation: The internal architecture of 80386 is divided into three sections namely, central processing unit, memory management unit and bus interface unit.

2. The central processing unit has a sub-division of
a) memory unit and control unit                b) memory unit and ALU
c) execution unit and instruction unit       d) execution unit and memory unit View Answer
Answer: c Explanation: The central processing unit is further divided into execution unit and instruction unit.

3. The unit that is used for handling data, and calculate offset address is
a) memory management unit                   b) execution unit
c) instruction unit                                    d) bus interface unit View Answer
Answer: b Explanation: The execution unit has eight general purpose and eight special purpose registers, which are either used for handling the data or calculating the offset addresses.

4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit                                  b) execution unit
c) instruction unit                                                   d) barrel shifter View Answer
Answer: c Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code queue, after decoding them so as to pass it to the control section, for deriving the necessary control signals.

5. The unit that increases the speed of all shift and rotate operations is
a) memory management unit                          b) execution unit
c) instruction unit                                           d) barrel shifter View Answer
Answer: d Explanation: The barrel shifter speeds up all shift and rotate operations.

6. The memory management unit consists of
a) segmentation unit                         b) paging unit
c) segmentation and paging units    d) none of the mentioned View Answer
Answer: c
Explanation: The memory management unit consists of a segmentation unit and a paging unit.

7. The segmentation unit allows
a) maximum size of 4GB segments               b) use of segment address components
c) use of offset address components              d) all of the mentioned View Answer
Answer: d Explanation: The segmentation unit allows the use of two address components. They are: segment and offset for relocation and sharing of code and data.

8. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit                                   b) execution unit
c) paging unit                                             d) instruction unit View Answer
Answer: c Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.

9. The paging unit works under the control of
a) memory management unit                              b) segmentation unit
c) execution unit                                                 d) instruction unit View Answer
Answer: b Explanation: The paging unit works under the control of segmentation unit; i.e. each segment is further divided into pages.

10. The unit that provides a four level protection mechanism, for system’s code and data against application program is
a) central processing unit                      b) segmentation unit
c) bus interface unit                              d) none of the mentioned View Answer
Answer: b Explanation: The segmentation unit provides a four level protection mechanism, for protecting and isolating the system’s code and data, from those of the application program.

11. The unit that has a prioritize to resolve the priority of the various bus requests is
a) bus sizing unit                                      b) data buffer
c) bus control unit                                   d) execution unit
View Answer
Answer: c Explanation: The bus control unit has a prioritize to resolve the priority of the various bus requests.

12. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit                                     b) data buffer
c) bus control unit                                   d) execution unit
View Answer
Answer: b Explanation: The data buffer interfaces the internal data bus with the system bus.

13. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit                                          b) bus driving unit
c) address driver                                          d) bus driver
View Answer
Answer: c Explanation: The address driver drives the bus enable and address signals A0-A31.

14. Which of the following pin when activated, allows address pipe-lining?
a) ADS         b) NA              c) AP                  d) none of the mentioned
View Answer
Answer: b Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus cycles.

15. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD                   b) HLDA            c) READY           d) PEREQ
View Answer
Answer: c Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of slow devices with the CPU.

16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY          b) NMI             c) HLDA              d) PEREQ
View Answer
Answer: d Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data word for the coprocessor.

17. The pipeline and dynamic bus sizing units handle
a) data signals                       b) address signals
c) control signals                  d) all of the mentioned View Answer
Answer: c Explanation: The pipeline and dynamic bus sizing units handle the related control signals.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Register Organisation of 80386 -1”.
1. The 16-bit registers are available with their extended size of 32 bits, by adding the registers with a prefix of
a) X         b) E               c) 32           d) XX
View Answer
Answer: b Explanation: A 32 bit register, known as extended register, is represented by the register name with a prefix of E.

2. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP      b) FSP            c) SP        d) none of the mentioned
View Answer
Answer: c Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP, SI and DI represent the lower 16-bits.

3. Which of the following is a data segment register of 80386?
a) ES    b) FS       c) GS        d) all of the mentioned
View Answer
Answer: d Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS, ES, FS and GS are the four data segment registers.

4. The register width used by the 32-bit addressing modes is
a) 8 bits            b) 16 bits             c) 32 bits            d) all of the mentioned
View Answer
Answer: d Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.

5. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag           b) RF flag                 c) VM and RF flag          d) none of the mentioned
View Answer
Answer: c Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register of 80386.

6. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode  b) protected mode    c) either virtual or protected mode    d) all of the mentioned
View Answer
Answer: b Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is to be set only when the 80386 is in protected mode.

7. In protected mode of 80386, the VM flag is set by using
a) IRET instruction                                               b) task switch operation
c) IRET instruction or task switch operation       d) none of the mentioned
View Answer
Answer: c Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only in the protected mode.

8. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set            b) VM flag is cleared          c) RF is cleared           d) RF is set
View Answer
Answer: d Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.

9. The RF is not automatically reset after the execution of
a) IRET            b) POPA             c) IRET and POPF       d) IRET and PUSHF
View Answer
Answer: c Explanation: The RF is automatically reset after the execution of every instruction, except for the IRET and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL and INT instructions causing a task switch.

10. The segment descriptor register is used to store
a) attributes          b) limit address of segments           c) base address of segments
d) all of the mentioned
View Answer
Answer: d Explanation: The segment descriptor register is used to store the descriptor information like attributes, limit and base addresses of segments.